Once the design is ready it is needed to be verified by the designer itself before submitting it for review. We have categorized the checklist in multiple sections for a systematic checking. There are many details that go into making a successful first – run design, and this checklist helps prevent bugs from marrying a healthy design otherwise.
We have tried to be as elaborate as possible, yet engineers are encouraged to add more checkpoints for better results. The idea is for engineers and technicians to share experiences and create a detailed checklist that can be tailored to meet their specific needs by the individual designer.
Before exporting your schematic to create a PCB, you must verify the design and fix errors in the schematic first. It is significantly more difficult to fix errors later (either during the PCB layout stage or after manufacturing) than to spend the time double-checking the schematic first.
Design for Function and Performance
- Check symbol pinouts against the data sheet, paying special attention to the part package (e.g., chips often come in multiple physical packages with different pin numbers)
- Check connector pinouts and orientation (top or bottom of board, inversion of pins)
- Check the data sheet for each part to ensure all support circuitry (e.g., external resistors for configuration) is present
- If an external oscillator or crystal is used, check that all support circuitry is present (e.g., low-ESR X7R capacitors)
- Check that crossing wires that should be connected have a dot at the intersection, and those that should not be connected do not have a dot
- For ICs, check that all power and ground pins are connected
- Run the schematic design rules check and resolve all errors
Design for Reliability
- When using an analog to digital converter, it's a good idea to filter the signal in hardware first with a band pass filter. This helps eliminate spurious noise that can corrupt your readings
- De-bounce all mechanical switches in hardware
- Check that all resistors have a wattage listed, and that wattage has at least a 50% margin
- Check that all capacitors have a working voltage listed, and that working voltage has at least a 25% margin
- Add a fuse to each power rail to help protect the circuit against accidental damage (e.g., shorting power and ground). Buy extra fuses.
For ICs, make sure:
- Bypass/decoupling capacitors are present for each chip. (0.1 uF ceramic for every power pin AND 1 uF, 10 uF, or 100 uF tantalum for every 10 to 20 ICs) (see Bypass Capacitor Basics page)
- Pull up or pull down resistors are used, rather than hardwiring signal pins to power planes
- Pull up or pull down resistors are used on all unused IC inputs. One exception is microcontrollers, which should have unused I/O pins tied to test points
Design for Testing
- Critical signals are connected to headers and/or test points to facilitate easy testing and debugging
- Test points are attached to key signals or unused pins that may be useful in the future (e.g., extra microcontroller I/O pins)
- Zero-ohm resistors are used in series on critical nets (e.g., power nets) to allow easy troubleshooting of circuit subsystems
Design for Manufacturability/Service/Accessibility/Assembly
- Group components into labeled modules matching with the labels on the block diagram
- There is a way to connect power to each board (e.g., a connector)
- Connectors are used for off-board connections. Always include at least one ground wire/signal return path in connections between boards
- Check that in-system programming headers exist and include any required support circuitry (e.g., pull-up resistors). This information can be found in the microcontroller data sheet.
- Check that all components have a real part number (meaning you could copy and paste the part number into a distributor's search engine and return one part). Resistors, capacitors, and inductors can be labeled with their values (e.g., 0.1uF) instead of the full part number.
- Add a surface-mount LED and current-limiting resistor to each power rail to provide a visual indication that the power supplies are on
In most cases, 90% of design is based on some reference design or previous design make sure all essence of the original design is captured properly.
Check with the high-level documentation if all the requirements are translated into design properly or not.
General checklist
- All unused inputs terminated.[24]
- For buses, ensure bus order matches device order.[25]
- All no-connect pins on IC’s should be labelled NC.[26]
- Unpopulated parts annotated and enclosed by the dashed-line box on schematics.[27]
- Wires exist between all connected pins/ports (no direct pin/pin connections).[28]
- Avoid direct connect of mode pins or no-connect bus lines to GND or VCC so PCB reworks options are maximal (add 0-ohm resistor).[29]
- Connect DIP switches and other grouped I/O to ports in a logical way, i.e. LS bit to LS bit and MS bit
to MS bit.[30] - Polarized components checked for connected polarity.[31]
- Check pin numbers and pin type assignment of all custom-generated parts.[32]
- Check if no dot is present on any pin after ERC run.[33]
- Check for single nets.[34]
- Check for multi-driven nets.[35]
- Check all the specific instructions are noted down near each component/net that can be utilized in layout e.g. High-frequency net, matched impedance net value, thermal requirement etc.[36]
- Mechanical artefacts e.g. a screw, heatsink etc. should be added in schematic and it should be decided if they are connected to any
net or isolated.[37]
Design related checklist
- Check with the high-level documentation if all the requirements are translated into design properly or not. [1]
- In most cases, 90% of design is based on some reference design or previous design make sure all essence of the original design is captured properly. [2]
- Make sure the remaining 10% of the schematic is properly simulated or logically evaluated for proper functionality. [3]
- Race conditions are checked. [4]
- Each IC has a predictable or controlled power-up state. [5]
- Check the datasheet fine print and app notes for weird IC behaviours.[6]
- Amplifiers checked for stability.[7]
- Oscillators checked for reliable startup.[8]
- Pull-ups on all open collector / open drain outputs.[9]
- Reset circuit design reliability checked, for both glitch-free and consistent operation.[10]
- Check time delays and slew rates of opamps used as comparators.[11]
- Check opamp input over-drive response for unintended output inversion.[12]
- Check common mode input voltages on opamps.[13]
- Voltage ratings of components checked.[14]
- Output driver current checked.[15]
- Setup, hold and access times for data and address buses validated.[16]
- Use of baud rate friendly clock source for devices that have serial ports.[17]
- Mating connectors on different assemblies checked for the same pinout.[18]
- Off-board connectors identification for all signals, even if not used on this design.[19]
- Card edge connectors identification for the mating parts.[20]
- Ground made first and breaks last for hot pluggability in the connector.[21]
- Calculate current consumption properly for selection of PMIC/LDO.[22]
- Verify if every signal has a proper return path available. There should be no break in ground signal.[23]
Preferred component reference designators.[93]
- R: fixed resistor
- RN: resistor network
- RV:
variable resistor - C: capacitor
- CN: capacitor network
- CV:
variable capacitor - L: inductor
- Q: transistor, FET, SCR, TRIAC
- D: diode, rectifier, Zener, LED
- DL: multisegment display (any type)
- VR/U: voltage regulator
- U:
integrated circuit - J: socket, jack (female)
- P: plug (male)
- JP jumper (pins, trace, or wire)
- Y/X: crystal
- M: modular subassembly,
daughter board - S: mechanical switch
- F: fuse
- FB: ferrite bead
- FL: filter
- T: transformer
- KB: keyboard
- BT: battery
Bill of material(BoM) related checklist
- Each component has quantity, reference designator and description.
- Suggested and alternate manufacturer(s) listed.
- Price and availability checked for each component.
- Part is verified against schematic value and assigned footprint.
Power Integrity related checklist
- Adequate bypass cap for each IC.[42]
- Electrolytic and tantalum capacitors checked for no reverse voltage.[43]
- Check hidden power and ground connections.[44]
- Sufficient power rails for
analog circuits.[45] - Sufficient capacitance on low dropout voltage regulators.[46]
- High PSRR regulator selection for sensitive and high-speed circuitry.[47]
- No power or ground loop exists.[48]
- No hidden ground connection between isolated sections.[49]
- Check for the ferrite bead/resistor current carrying capacity used in power line.[50]
- Ensure that MLCC used are having at least twice the voltage rating than required.[51]
- Ensure Tantalum/Electrolytic capacitors used are having at least 1.5 times rated voltage than required.[52]
- Ensure that high-frequency high power devices powered by a separate regulator with(/or) adequate filtering.[53]
Electro-magnetic compatibility related checklist
- All outside world I/O lines filtered for RFI.[54]
- All outside world I/O lines protected against static discharge.[55]
- Consider signal rate-of-rise and fall for noise radiation.[56]
- Separate
analog signals from noisy or digital signals.[57] - Under-utilization of gates on multi-gate parts checked.[58]
- Clock lines with series termination and parallel termination component locations present even if not populated.[59]
- Piezo elements generate voltages (when shocked) that can destroy their drivers — check for susceptibility.[60]
- Isolation is not always necessary for design, use engineering judgement to decide. Magnetic isolation increases susceptibility.[61]
Reliability related checklist
- Check for input voltages applied with power off and CMOS latch-up possibilities.[62]
- Check maximum power dissipation at worst-case operating temperatures. find if heat-sink is required.[63]
- Determine the effect of losing each of multiple grounds on a connector.[64]
- Automotive powered devices must withstand 60 to 100-volt surges.[65]
- Check for voltage transients and high voltages on FET gates.[66]
- Estimate the total worst case power supply current.[67]
- Ensure resistors are operating within their specified power range plus a safety factor.[68]
- Check for low impedance sources driving tantalum caps which can cause premature failure.[69]
- Avoid reverse base-emitter current/voltage on bipolar transistors.[70]
Test ability checklist
- Ability to disable watchdog timer for testing, diagnostics and emulation.[71]
- Ability to isolate/ off the power supply for a certain section of design to test.[72]
- Diagnostic resources by design (LEDs, serial ports, etc.) even if unpopulated by default.[73]
- Test points on power and ground lines.[74]
Life-cycle checklist
- Part obsolescence review.[75]
- Replacement part compatibility with software requirements.[76]
- Electronic and Schematics
- all unused inputs terminated
- race conditions checked
- Darlington outputs (1.2v low) driving logic inputs
- mating connectors on different assemblies checked for same pinout
- all outside world I/O lines filtered for RFI
- all outside world I/O lines protected against static discharge
- bypass cap for each IC
- voltage ratings of components checked — as was not done in the on-board computer in my 1990 Geo Tracker, apparently manufactured by Mitsubishi, where capacitor C4 was rated at 47uf/50V across an automotive rail which can easily see larger spikes. Other owners reported such problems in vehicles from 1990 to 1995, with the capacitor spewing electrolyte onto the conformally coated PCB, corroding conductors in the vicinity. Hats off to Mitsubishi for ignoring a simple checklist item for five years and who knows how many hundred thousand vehicle shipments, and who knows how many in-service failures.
- each IC has predictable or controlled power-up state
- file name on each sheet
- dot on each connection
- minimum number of characters in values
- consistent character size for readability
- schematics printed at a readable scale
- all components have reference designators and values
- special PCB or parts list information entered for each component, if required
- polarized components checked
- electrolytic and tantalum capacitors checked for no reverse voltage
- power and ground pins listed for each component with hidden power pins
- check hidden power and ground connections
- title block completed for each sheet
- ground made first and breaks last for hot pluggability
- pullups on all open collector outputs
- sufficient power rails for analog circuits
- LM324 and LM358 outputs loaded to prevent crossover distortion
- amplifiers checked for stability
- oscillators checked for reliable startup
- consider signal rate-of-rise and fall for noise radiation
- check for input voltages applied with power off and CMOS latchup possibilities
- reset circuit design reliable, both glitch-free and consistent; tested with slow power supply fall time
- separate analog signals from noisy or digital signals
- ability to disable watchdog timer for testing and diagnostics and emulation
- sufficient capacitance on low dropout voltage regulators
- setup, hold, access times for data and address busses
- check the data sheet fine print and apnotes for weird IC behaviors
- determine effect of losing each of multiple grounds on a connector
- automotive powered devices must withstand 60 to 100 volt surges
- check maximum power dissipation at worst-case operating temperatures
- check time delays and slew rates of opamps used as comparators
- check opamp input over-drive response for unintended output inversion
- check common mode input voltages on opamps
- check for voltage transients and high voltages on FET gates
- check failure modes and effects of failed power semiconductors
- estimate total worst case power supply current
- check pin numbers of all custom-generated parts
- for buses, ensure bus order matches device order
- ensure resistors are operating within their specified power range plus safety factor
- resistor power ratings derated for elevated ambient temperatures
- electrolytic/tantalum capacitor temperature/voltage derating sufficient for MTBF
- check for low impedance sources driving tantalum caps which can cause premature failure
- avoid reverse base-emitter current/voltage on bipolar transistors
- use of baud rate friendly clock source for devices that have serial ports
- ~IOR and ~IOW strobes on UARTs are typically incompatible with timings of signals readily available on many processors
- ROHS compliance requirement review
- part obsolescence review
- replacement part compatibility with software requirements: “top-boot vs. bottom boot FLASH”, UART compatibility, SPI memory timing and addressing for different sized parts
- all PCB signal changes noted to the software geeks
- all no-connect pins on IC’s should be labelled NC
- text should not overlap wire or symbol graphics on schematics
- busses with off-page destinations present with title at page margin
- card edge connectors identify mating part
- page title present and consistent on all pages if not in title block
- under-utilization of gates on multi-gate parts checked
- off board connectors identify all signals even if not used on this design
- unpopulated parts annotated and enclosed by dashed-line box on schematics
- wires exist between all connected pins/ports (no direct pin/pin connections) if capture package does not like such connections
- symbols identify open collector/drain pins and internal pulled up/down pins
- clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination
- avoid direct connect of mode pins or no-connect bus lines to GND or VCC so PCB rework options are maximal
- diagnostic resources by design (leds, serial ports, etc.) even if unpopulated by default
- pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name)
- connect DIP switches and other grouped I/O to ports in a logical way, LS bit to LS bit, MS bit to MS bit
- piezo elements generate voltages (when shocked) that can destroy their drivers — check for susceptibility
- preferred component reference designators
- R fixed resistor
- RN resistor network
- RV variable resistor
- C capacitor (network, fixed or variable)
- L inductor
- Q transistor, FET, SCR, TRIAC
- D,CR diode, rectifier, Zener, varicap, LED
- DL multisegment display (any type)
- VR,Q,IC voltage regulator
- U,IC integrated circuit
- J socket, jack (female)
- P plug (male)
- JP jumper (pins, trace, or wire)
- Y,X crystal
- M modular subassembly, daughter board
- S mechanical switch
- F fuse
- FL filter
- T transformer
- KB keyboard
- B,BT battery
- PCB Design
- hole diameter on drawing are finished sizes, after plating.
- finished hole sizes are >=10 mils larger than lead
- silkscreen legend text weight >=10 mils
- pads >=15 mils larger than finished hole sizes
- place thruhole components on 50 mil grid
- no silkscreen legend text over vias (if vias not soldermasked) or holes
- soldermask does or does not cover vias
- all legend text reads in one or two directions
- components labeled left-right, top-bottom
- company logo in silkscreen legend
- company logo in foil
- copyright notice on PCB
- date code on PCB
- PCB part number
- assembly part number on PCB
- all polarized components point same way
- components >=0.2″ from edge of PCB
- ground planes where possible
- test pad or test via on every net to allow in circuit test
- test pads 200 mils from edge of board
- mounting holes electrically isolated or not
- mounting holes with or without islands
- proper mounting hole clearance for hardware
- all polarized components checked
- no acute inside angles in foil
- traces >= 20 mils from edge of PCB
- PCB revision on silkscreen legend
- assembly revision blank on silkscreen legend
- serial number blank on silkscreen legend
- soldermask swell checked
- thru hole drill tolerance noted
- thru hole soldermask tolerance noted
- thru hole route tolerance noted
- thru hole silkscreen legend tolerance noted
- drill legend shows all symbols and sizes
- mounting holes matched 1:1 with mating parts
- automated netlist check
- manual netlist check
- check netlist for nodes with only one connection
- CAD design rule check
- drill origin is a tooling hole
- checkplots sent with disk based photoplot files
- NC drill and photoplot file language format noted
- tools on drill plot and NC drill file cross checked
- soldermask over bare copper noted if needed
- PCB thickness, material, copper weight noted
- trace and space geometry noted
- printed drill report sent with checkplots
- printed aperture table sent with checkplots
- photoplot files checked in file viewer
- test coupon on PCB containing minimum geometry features
- trace width sufficient for current carried
- minimum component body spacing
- SMD pad shapes checked
- visual references for automated assembly
- tooling holes for automated assembly
- sufficient clearance for high voltage traces
- component and trace keepout areas observed
- high frequency circuitry precautions observed
- thermal reliefs for internal power layers
- solder paste mask openings are proper size
- blind and buried vias allowed on multilayer PCB
- PCB layout panelized correctly
- panelized PCB fits test and manufacturing equipment
- sufficient clearance for socketed ICs
- SMD component orientation arbitrary or consistent
- ensure pin 1 interpretation and orientation consistent among all connectors of a given type on the board
- clearance for IC extraction tools
- clearance for emulator adapter or pod
- clearance for sockets for ICs during proto phase
- standoffs on power resistors or other hot components
- digital and analog signal commons joined at only one point
- EMI and RFI filtering as close as possible to exit and entry points in shielded areas
- layout PCB so that any rework or repair of a component does not require removal of other components
- extra connector and IC pins accessible on prototype boards, just in case
- check all power and ground connections to ICs
- provide ground test points, accessible and sized for scope ground clip
- potentiometers should increase controlled quantity clockwise
- check hole diameters for odd components: rectangular pins, spring pins
- check the orientation of all connectors using actual connector/cable
- bypass capacitors located close to IC power pins
- all silkscreen text located to be readable when the board is populated
- all ICs have pin one clearly marked, visible even when chip is installed
- high pin count ICs and connectors have corner pins numbered for ease of location
- silk screen tick marks for every 5th or 10th pin on high pin count ICs and connectors
- verify that all series terminators are located near the source
- place I/O drivers near where their signals leave the board
- high frequency crystal cases should be flush to the PCB and grounded
- check for traces running under noisy or sensitive components
- check IC pin count on layout vs schematic
- no vias under metal-film resistors and similar poorly insulated parts
- check for traces which may be susceptible to solder bridging
- maximize distances between features where possible
- check for dead-end traces
- check for power not shorted to ground
- ensure schematic software did / did not separate Vcc from Vdd, Vss from GND as needed
- provide multiple vias for high current and/or low impedance traces
- coupons for board part number, anti-static warning, QC markings
- PCB has ground turrets, power rail test points, and test points for for important signals, all labeled
- PCB Assemblies
- miscellaneous parts on bill of materials and assembly notes for same: hardware, heat sinks, heat sink compound or composite insulators, IC sockets, consumables
- assembly notes for all special operations
- conformal coating
- special static handling precautions required during assembly and test
- Wired Assemblies
- wire gauge checked for compatibility with each termination
- cable ties or lacing cord shown where needed
- length &color of each wire indicated
- notes about application of wire terminations (technique, heat shrink tubing, amount of solder, crimp force, tools, etc.)
- Parts Lists
- each component has quantity, reference designator and description
- list qualified part numbers for special devices
- suggested and alternate manufacturer(s) listed
- object/binary code and method/programmer specified for each programmable device
- price and availability checked for each component
- Mechanical Drawings
- standard title block and border used
- no dimensions on the material
- every feature must have X and Y dimension, along with radius, diameter, etc.
- every hole must be checked for alignment with mating hole(s) in other parts
- check every hole diameter
- tolerance for sheet metal feature position noted
- tolerance for sheet metal hole size noted
- specify material
- specify finish
- specify units
- specify debur or brush
- details for special operations
- file name on each sheet
- CAD layers shown on drawing
- all hardware specified and listed on parts list
- screw lengths checked; extra thread required for fasteners (nut, lockwasher, washer)
- hole diameters checked for each screw
- tapped hole thread details indicated
- Software
- each version archived for future reference
- loops checked for terminating conditions
- communications timeouts checked
- all branches tested
- revision history noted for all changes
- CPU utilization measured
- interrupt response time measured
- interrupt execution time measured
- naming conventions consistent and relevant to humans
- adherence to coding style standards
- power-up, power-down considerations
- unused vectors trapped to restart or damage control routine
- unused ROM space loaded with trap or restart instructions
- warm and cold reset differences
- nonvolatile memory corruption possibilities checked during power-up, power-down, and program-gone-wild conditions
- design notes within or separate from code
- check for FIFO and buffer overruns
- check critical timer driver code
- check for odd address usage on 16/32 bit micros, especially an odd stack pointer
- use a LINT utility on C programs to find subtle problems
- program’s data structures contain version numbers to detect program version upgrades and translate the structures’ formats
- Testability
- test points on PCBs for critical circuits, hard to reach nets
- test pads for in-circuit or bed-of-nails functional testing
- test pads on a regular grid
- test procedure written for each test phase
- special test arrangements and connectors for testing
- Maintainability
- easy disassembly and reassembly
- fuses accessible and labeled
- self test mode
- spare parts available
- status LEDs on PCB
- event logging of exceptional conditions
- vibration tolerance of entire assembly and individual modules
- surge current magnitude through semiconductors within rating
- thermal cycling excursions internal to components and assemblies within acceptable limits
- capacitors mounted below or away from heat-dissipating devices such as transformers
- resistance and tolerance of entire product to static discharge via any path
- Safety
- fuse and circuit breaker size and characteristics
- fuse sizes marked near fuse holder
- room to remove fuse without damaging other components
- spare fuse storage
- shock hazards
- radiated energy warnings and shields
- applicable standards checked
- protection against liquids and foreign objects
- Documentation
- end-user instructions: unpacking, how to use, warranty, service, troubleshooting
- service manual: troubleshooting procedures, parts lists, helpline info
- design notes: why significant design decisions were made the way they were
- other info that may be lost if designers depart the organization
Checklist for error-free optimized PCB layout
Preliminary checks
Schematic review completed, including pin swaps done during layout.
Layout DRC is run in the tool and it is found 100% clean.
Footprint checks
Verify schematic symbol matches the selected package.
Confirm pinout diagram is from the top or bottom of the package.
Print PCB on paper with a 1:1 ratio and match with physical parts.
Obtain the 3D model and check against footprints.
Soldermask apertures on all SMT lands and PTH pads.
SMD pad shapes checked
Thermal reliefs for internal power layers.
It’s better to create a do-not place/do-not route area with every part of footprint design. In this way, the DRC tool will easily catch any interference between the parts.
No uncapped vias in pads. (except low-power QFNs where some voiding is acceptable)
QFN paste prints segmented.
Solder paste small pads 100% size, larger pads reduced to avoid excessive solder volume.
Adequate clearance around pads (typically 50 um).
Solder mask does or does not cover vias.
Solder mask swell checked.
Part placement
Check if part orientation is consistent.
Components >=0.2″ from edge of PCB.
Appropriate clearance is provided between the parts.
Check the direction of all polarized components.
Every IC has bypass capacitors near the power pin placed near to the body. (A direct connection, without via is preferable but in some cases(e.g. BGA components) it is not possible.)
Verify all series termination is located near source.
Verify all parallel termination is located near the sink.
I/O drivers are placed near connectors.
RFI/EMI filtering is provided as close as possible to entry/exit of the board.
Placement should be in such a way that during repair any IC should not be removed to replace others.
SMD component orientation arbitrary or consistent.
Ensure pin 1 interpretation and orientation consistent among all connectors of a given type on the board.
Preferably put all wired connectors including power input to one side of the board. (There should be no high-speed circuit between two wired connectors, else they tend to make unwanted antenna easily.)
Routing check
Power
Provide multiple vias for high current and/or low impedance traces.
Sufficient width for planes/traces for required current.
Sufficient clearance for high voltage traces.
Minimal slots in planes from via anti-pads.
Check all power and ground connections to ICs.
Check for power not shorted to ground.
General
No vias/trace under metal-film resistors and similar poorly insulated parts.
Check for dead-end traces, unless used on purpose.
Check crystal connections are short.
High-frequency crystal cases should be flush to the PCB and grounded.
Check for traces running under noisy or sensitive components.
Digital and analog signal commons joined at only one point.
Routing should be away from PCB edge inside the ground boundary.
Automated and manual netlist check.
Trace and space geometry noted.
No sharp turns in traces.
No acute angles in planes.
Check if there are any Isolated copper nets.
Blind and buried vias allowed on multilayer PCB.
Sensitive analog
Guard ring / EMI cages provided if needed.
Physically separated from high current SMPS or other noise sources.
MLCC can act as a sound sensor in the presence of loud audio source.
High-speed
Ensure that all high-speed signal traces run over their own ground/power planes. Do not allow a digital signal to travel over the analog plane unless it goes to a device in that area and then follows the digital ground trace devices to minimize the loop and therefore noise.
If there are any slots or gaps in the Ground/Power plane, no high-speed signals should run over them.
Sufficient clearance to potential aggressors to minimize the cross-talk.
Check length matching if required.
Trace width checked for controlled impedance.
Check pad width on connectors and add plane cutouts if needed to minimize impedance discontinuities.
For high-speed signals minimise track stubs (to below the critical length – ideally < 6.5mm, no more than 12mm for a 1ns rise time signal).
Ideally, high-speed connectors should have the ground plane getting through between pins to avoid signal return paths having to go round the connector to a ground pin on it.
Differential Pair
Differential pair tracks are spaced based on impedance calculation?
Skew is matched?
Clearance from non-coupled nets provided?
Mechanical check
LEDs, buttons, and other UI elements on the outward-facing side of the board.
Stress-sensitive components (MLCC) oriented to reduce the effect of stress.
Clearance around large ICs for heatsinks/fans if required.
Clearance around pluggable connectors for mating cable/connector.
Clearance around mounting holes for screws.
Plane keep-outs and clearance provided for shielded connectors, magnetics, etc.
Confirm PCB dimensions and mounting hole size/placement against enclosure or card rack design.
Verify the mounting hole connection/isolation.
Hole diameter on the drawing is finished sizes, after plating.
Components not physically overlapping/colliding.
Clearance provided around solder-in test points for probe tips.
Finished hole sizes are >=10 mils larger than lead.
All tolerance noted with reasonable approximation.
Pads >=15 mils larger than finished hole sizes.
Test pads 200 mils from the edge of the board (unless required by design).
If the circuit board is going into a tight-fitting enclosure, have component heights and other mechanical keep-outs been accounted for?
Does the fabrication drawing show the PCB outer dimensions?
Mounting holes electrically isolated or not.
Mounting holes with or without islands.
Proper mounting hole clearance for hardware.
Mounting holes matched 1:1 with mating parts.
Drill legend shows all symbols and sizes.
Check plots sent with disk-based photo plot files.
NC drill and photo plot file language format noted.
Tools on drill plot and NC drill file cross-checked.
Solder mask over bare copper noted if needed.
PCB thickness, material, copper weight noted.
Printed drill report sent with check plots.
Printed aperture table sent with check plots.
Photoplot files checked in the file viewer.
Test coupon on PCB containing minimum geometry features.
Thermal check
Solid connections used to planes if heatsinking.
Ensure thermal balance on components of SMT chips to minimize the risk of stoning.
Do high power components have adequate heat sinking using PCB copper heatsink or mechanical heat sink? (check data-sheet of thermal requirements. In case of FPGA perform power estimation using tool provided).
Standoffs on power resistors or other hot components.
Silkscreen check
Silkscreen legend text weight >=10 mils.
No silkscreen legend text over vias (if vias are not solder masked) or holes.
All legend text reads in one or two directions.
Components labelled left-right, top-bottom.
Company logo in silkscreen legend.
Company logo in foil.
The copyright notice on PCB.
Date code on PCB.
PCB part number.
PCB revision on silkscreen legend.
Assembly revision blank on silkscreen legend.
Serial number blank on silkscreen legend.
All silkscreen text located to be readable when the board is populated.
All ICs have pin one clearly marked, visible even when the chip is installed.
High pin count ICs and connectors have corner pins numbered for ease of location.
Silkscreen tick marks for every 5th or 10th pin on high pin count ICs and connectors.
Coupons for board part number, anti-static warning, QC markings.
PCB has ground turrets, power rail test points, and test points for important signals, all labelled.
Design for Testing(DFT)
Test pad or test via on every net to allow in-circuit test.
Provide ground test points, accessible and sized for scope ground clip.
Does the board include adequate structures or connectors for firmware load or functional test?
If the board is intended for high volume manufacturing, does the design include bottom side solder mask openings to allow for a bed of nails in-circuit test?
Design for Manufacturing(DFM)
Fabrication
All design rules within the manufacturer’s capability.
Minimize the use of vias/traces that push fab limits.
Controlled impedance specified in fab notes if applicable.
Stackup verified with the manufacturer and specified in fab notes.
Board finish specified in fab notes.
If penalizing, add panel location indicators for identifying location-specific reflow issues.
Layer number markers specified to ensure correct assembly.
Panelized PCB fits test and manufacturing equipment.
Board outline indicated on the fabrication drawing and solder mask top (SMT) layer.
Export Gerber/drill files at the same time to ensure consistency.
Visually verify final CAM files to ensure no obvious misalignments.
Assembly
Visual references for automated assembly.
Tooling holes for automated assembly.
Are surface mount components used wherever possible instead of through holes? This improves assembly automation, quality, and manufacturing cost.
For all through-hole components, are the bottom side copper rings nice and wide (copper diameter >= drill diameter + 40 mils) to allow for easy wave/hand soldering? Pins that are tight pitch can use ovals or rectangular annular rings?
Are bottom side SMT components appropriately spaced (> 250 mils) away from through-hole pins?
Do all traces and components have sufficient clearance (>30 mils) away from the edge of the board?
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